1. Field of the Invention
The subject invention relates generally to the design and fabrication of semiconductor devices and, more particularly, to a technique for the formation of isolation regions between active areas in a semiconductor substrate, wherein the area available for the formation of active devices is optimized and the threading of crystalline defects to the substrate surface is diminished.
2. Related Art
The design and fabrication of semiconductor devices routinely require that isolation regions be provided in order to physically and electrically decouple active areas that are formed in a semiconductor substrate. Specifically, isolation is necessary to prevent conduction in the form of leakage current between devices. In the context of CMOS technology, it is regularly necessary to isolate areas of the substrate that contain N-channel transistors from areas that contain P-channel transistors. That is, isolation areas are interposed between, for example, an N-channel MOS transistor that is formed in a P-type well and an adjacent P-channel MOS transistor that is formed in an N-type well or substrate. Similarly, isolation is required between adjacent MOS transistors of the same conductivity type. For any semiconductor technology, the metrics applicable to isolation techniques include: circuit density, process complexity, yield, planarity and severity of parasitic effects.
A standard, and somewhat primitive, approach to the provision of isolation between active devices in a semiconductor substrate relies on the local oxidation of silicon (LOCOS) to isolate active areas. FIG. 1 is a cross-sectional view of a device 10 formed with a standard LOCOS process. The LOCOS process begins with the formation of a thin oxide layer 11 on the semiconductor substrate 12, followed by the deposition of a thin Si3N4 film 13. Subsequent to patterning the nitride layer with photoresist, a field implant is performed. The photoresist is then stripped and the substrate is oxidized. The nitride serves as a diffusion barrier so that oxidation is inhibited in selected regions that ultimately become active areas of the semiconductor device.
As is well known, the LOCOS process results in a “bird's beak” isolation profile that is characterized by a surface bump and a narrowing tail into the active area. The length of the bird's beak reduces the effective width of the active area and also contributes to the narrow-channel effect. The narrow-channel effect is known to skilled artisans as a subtle consequence of the LOCOS process, resulting from the encroachment by the field oxide into the active area. Specifically, diffusion of dopants from the implanted field oxide areas into the edges of the active region (illustrated by the dashed lines in FIG. 1) tends to increase the threshold voltage of the device. Furthermore, diffusion of field oxide dopants reduces the transistor channel width, thereby reducing the device drive current. The narrow-channel effect is especially detrimental in extremely dense technologies such as memories. For these and other reasons, it appears clear that LOCOS, as well as it's derivative isolation techniques, is contraindicated as an isolation mechanism in designs with transistor densities greater than approximately 106/cm2.
Accordingly, alternative approaches have been developed in response to the shortcomings of LOCOS. One such alternative, trench isolation, is predicated on etching away part of the substrate and refilling the etched area (trench) with an insulator, almost invariably deposited oxide. It has been found that the profile of the isolation trenches influences a number of device performance parameters, including the level of leakage current that occurs at the junction between devices. For example, an isolation trench having substantially vertical sidewalls is susceptible to the formation of keyhole voids during subsequent filling of the trench with an oxide insulator. Keyholes (voids) adversely affect reliability and are not acceptable in the fabrication of semiconductor devices.
As an alternative to vertical trenching, tapered trenches have been implemented to extenuate the effects of keyholes during the formation of isolation regions. Tapered isolation trenches, such as the isolation trench depicted in FIG. 2, are formed that exhibit a profile having a width that varies inversely with the depth of the trench from the substrate surface. That is, the isolation trench is wider at the surface of the substrate than at a depth into the substrate.
As depicted in FIG. 2, pertinent aspects of a semiconductor device that incorporates tapered trench isolation include a substrate 21, on which there are formed a plurality of active areas 23. (Structural details regarding specific functional devices that may be formed in active areas 23 have been omitted here for the sake of brevity and clarity.) The active areas are mutually isolated by tapered trench structures 22. (Only one such trench structure is depicted.) Each trench structure 22 is defined by a pair of tapered sidewalls 221 that extend from surface 231 of a respectively adjacent active area on semiconductor substrate 21.
It has been determined that tapering of the isolation trench from wider at the surface to narrower at the bottom exacerbates the vulnerability of active devices to leakage between adjacent transistors. Tapering in this manner results in a reduction in the distance between adjacent transistors and is therefore attended by a greater susceptibility to leakage. Furthermore, when device dimensions are scaled, the dimensions of the isolation trenches are scaled proportionately. Both the width and the depth of the isolation trench must be reduced concomitantly in order to maintain the aspect ratio of the trench. Scaling therefore minimizes the distance between adjacent devices and further aggravates leakage effects. Tapered trenches also tend to compromise the packing density of devices on a wafer.
Reduction of the trench depth has also been entertained as a technique to obviate the effects of keyholes. That is, it has been found that keyholes can be avoided in the formation of isolation regions by reducing the aspect ratio of the isolation trench. However, reducing the isolation trench depth also diminishes the distance between adjacent transistors. As suggested above, in the event that more aggressive design rules are imposed, the trench depth must be scaled proportionally to maintain substantially the same aspect ratio in an effort to limit the generation of keyholes.
The above-identified difficulties associated with existing vertical trench isolation structures are, in large part, remediated by the isolation technique disclosed in U.S. Pat. No. 6,362,071, Method for Forming a Semiconductor Device With an Opening in a Dielectric Layer, that patent assigned to the assignee of this patent application. As may be seen in FIG. 3, the approach introduced there results in the formation of inverted isolation structures 32 that are disposed between active areas 31 on a semiconductor substrate 30. Each of the isolation structures 32 is a composite that comprises a bottom layer 321 on substrate 30, and a top layer 322 on bottom layer 321. Bottom layer 321 may be thermally grown silicon dioxide or may be an oxide formed by a chemical vapor deposition (CVD). Top layer 322 serves as a stop layer for an etching step or a chemical-mechanical polishing (CMP) step undertaken in the fabrication of the device. Examples of materials that are appropriate for top layer 322 include silicon nitride, aluminum oxide, or any other material effective to retard the relevant etching or CMP step.
A salient characteristic of the isolation structure depicted in FIG. 3 is the “inverted” nature of the isolation trench profile. Conventional vertical trench isolation structures are similar in that the exterior angle formed by a trench sidewall with the respectively adjacent active area is greater than 90 degrees (obtuse). This relationship may be seen in FIG. 2, where trench sidewall 221 forms an obtuse angle 24 with the surface 231 of active area 23. In contradistinction, the inverted structure of FIG. 3 results in a corresponding angle (between trench sidewall and surface of the active area) that is less than 90 degrees (acute). This geometry may be seen in FIG. 3, wherein the intersection of trench sidewall 323 with surface 311 forms an angle 33 that is less than 90 degrees. (A caveat is in order here. FIG. 2 and FIG. 3 imply a degree of sidewall sloping that has been exaggerated there solely for pedagogical purposes. With respect to both the conventional vertical trench structure of FIG. 2, as well as the inverted structure of FIG. 3, the degree of sidewall sloping off vertical is almost always less than 10 degrees and is, therefore, largely undetectable by visual inspection. For example, obtuse angle 24 is normally no greater than 100 degrees; acute angle 33 is normally no less than 80 degrees.)
In one embodiment, the inverted trench profile of FIG. 3 is realized through an etch process wherein a gas containing carbon and fluorine is combined with oxygen. The introduction of oxygen, with a carbon and fluorine containing gas, effects a resist erosion, thereby facilitating a tapered etch profile. Specific examples of gases that contain both carbon and fluorine and that may be used in the target process include: CHF3 CF4, C2F6, C3F8 and C4F8. Any one of a number of suitable commercially available etch chambers may be used in this process. A typical etch process condition is: 1100 W, 200 mtorr, 30 gauss, 50 sccm CHF3, 10 sccm O2, and 50 sccm Ar.
Although the salutary nature of the above-described inverted trench isolation technique cannot be gainsaid, a number of difficulties inhere therein. The dry plasma etching step that is required to form the inverted trench sidewalls presents a process control challenge. This is due in part to the nature of conventional dry plasma etches, which are customarily designed to produce anisotropic etch profiles, rather than the sloped profile dictated by the inverted trench. In addition, the inverted trench fabrication process that is described above has in practice been found to produce trenches that vary in width across the semiconductor wafer, causing the width of the associated active areas to vary accordingly. Finally, the linearly varying slope of the trench sidewalls has been correlated to threading of crystalline defects to the wafer surface. Although threading defects are in all instances undesirable, the minimization of threading dislocation density is particularly critical to SiGe epitaxial devices, in which an uppermost strained Si layer is formed to increase the mobility of holes in P-channel devices and the mobility of electrons in N-channel devices.
Accordingly, there remains a persisting need for improvement in isolation techniques available for semiconductor device fabrication. The desiderata attributable to a more nearly optional isolation structure include: maximization of active device density, ease of fabrication, provision of adequate isolation, resistance to the creation and propagation of crystalline defects, and uniformity across the semiconductor wafer.
Skilled artisans appreciate that elements in Drawings are illustrated for simplicity and clarity and have not (unless so stated in the Description) necessarily been drawn to scale. For example, the dimensions of some elements in the Drawings may be exaggerated relative to other elements to promote and improve understanding of embodiments of the invention.